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CIE: Wang Jian

published: 2016-12-16 11:46:23       hits: 

name : Wang Jian Sex: Male phone: 13880639846
email: wangjian3630@uestc.edu.cn office-address: Research Building, Hall B, 255
PH.D  Supervisor: No Master Supervisor: Yes
major: 081000信息与通信工程
Information and Communication Engineering
research interst:
02通信集成电路与信号处理(Integrated Circuits and Systems for Communication and Signal Processing)
Biography: He is an associate professor in UESTC. He interests in the on-chip multi-processors system, especially focuses on the design and optimization about on-chip communication infrastructure. 
Education experience: He received my B.S, M.S and PhD degree in 2005, 2008 and 2011 at University of Electronic Science and Technology, and He work as a post PhD in KTH, Sweden, from Jan. 2015 to Jan. 2016. 
Selected Publications: [1] J. Wang, Z. Lu and Y. Li. A High-Level Thermal Model-Based Task Mapping for CMPs in Dark Silicon Era. IEEE Transaction on Electron Devices, 2016, 63(9): 3406-3412  (SCI)
[2] J. Wang, Z. Lu and Y. Li. A New CDMA Encoding/Decoding Method for on Chip Communication Network. IEEE Trans. VLSI.2016, 24(4): 1607-1611. (SCI)
[3] J. Wang, Y. Li and J. Liao. A System-level Bandwidth Design Method for Wormhole Network-on-Chip. International journal of electronics. 2016, 103(11): 1928-1940 (SCI)
[4] Wang J, Li Y. A Novel Model of Computation for Software Synthesis Based on Data Frame Driving [J]. IETE Technical Review, 2015, 32(1): 70-78. (SCI: CB1IP)
[5] Jian Wang; Yubai Li; Huan Li; A Novel Parallel Viterbi Decoding scheme for NoC-based Software Defined Radio system. ETRI Journal, vol. 35, no. 5, Oct. 2013, pp. 767-774. (SCI:233WF)
[6] Jian Wang; Yubai Li; Huan Li; An Efficient Link Bandwidth Design Method for Application Specific Network-on-Chip. IETE Technical Review. Vol(30), no.2, 2013. pp: 102-107. (SCI:136HA)
[7] Jian Wang; Yubai Li; Huan Li; A Performance Analytical Strategy for Network-on-Chip Router with Input Buffer Architecture. Advances in Electrical and Computer Engineering. 2012, Vol(12), no.4. pp: 19-24. (SCI: 051LM).
[8] Jian Wang; Yubai Li; Qicong Peng; System-Level Buffer Allocation for Application Specific Network-on-Chip with Wormhole Routing. IETE Technical Review. 2012, vol(29), no.6, pp: 482-491. (SCI: 136HE)
[9] Jian Wang; Yubai Li; Qicong Peng; A Novel Analytical Model for Network-on-Chip using Semi-Markov Process. Advances in Electrical and Computer Engineering. 2011, Vol(11), no.1, pp: 111-120.(SCI: 739ZT).
[10] Jian Wang, Yubai Li, Chang Wu. An analytical model for network-on-chip with finite input buffer. Frontiers of computer science, vol(5), no.1, March 2011. pp: 126-134. (SCI: 789HL. EI: 20110913712653).
 
Books: "High Performance Compution in 4G communication system--Baseband algorithms parallelization and realization"