NOTES

Photo Gallery

VIDEOS

You are now here Home > Academics > Professors >

ES:Liao Yongbo

published: 2016-12-27 14:19:27       hits: 

name : Liao Yongbo Sex: Male phone: 0086-18615767741
email: lyb@uestc.edu.cn office-address: Research Institute Building 3002 , No. 2006, Xi Yuan Avenue, West High-tech Zone, Chengdu, Sichuan, 611731, P.R. China
PH.D  Supervisor:  No Master Supervisor: Yes
major: Electronic Science and Technology
research interest: Electronic Information Material and Devices
Biography: University of Electronic Science & Technology of China (UESTC)
Assistant Professor of School of Energy Science and Engineering, 2012-present
Lecturer of School of Microelectronics and Solid-State Electronics, 1999-2012
Education experience: Exchange Visiting Scholar, 2014.5-2015.5, University of Kansas
Ph.D. Microelectronics and solid-state electronics, 2007-2010, UESTC
M.S. Microelectronics and solid-state electronics, 2003-2006, Lanzhou University
B.A. Microelectronics and solid-state electronics, 1995-1999, UESTC
Selected Publications: 1. Y.B. Liao, X. Han, Z.J. Zhu, Y. Wang, S. Kang, “Vector mode based hardware acceleration and emulation for LDPC application”, International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol. 32, Issue 2, pp. 485 – 494, 2013. 
2. Liao Yongbo, Wang Yanhu, Yang Ming, "A temperature compensation circuit within constant current charging cycle", Applied Mechanics and Materials, 2013
3. Y.B.Liao, M. Yang, C. Bi, etc, “Constant Temperature Control of Solar Thermal Power Plant at Transient Variation of Sunlight”, Advanced Materials Research, Vol. 664, pp.1007-1011, Dec. 2012.
4. Y.B.Liao, P.Li, A.W.Ruan, W.Li, W.C.Li, “Design and Verification of An ALU-Based Universal FIR Filter”, International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol.29, Issue 2, pp. 317-326, 2010.
5. Yongbo Liao, Ping Li, Aiwu Ruan, "Novel scheme for full coverage test of logic resource faults in FPGA," Chinese Journal of Scientific Instrument, Vol. 31, No. 4, pp. 857-861, April 2010.
6. Yongbo Liao, Ping Li, Aiwu Ruan, Wenchang Li, Wei Li, "Test scheme for wide edge decoder in FPGA," Chinese Journal of Scientific Instrument, Vol. 31, No. 7, pp. 1638-1643, July 2010.
7. Yongbo Liao, Ping Li, Aiwu Ruan, Wei Li, Wenchang Li, Hui Li, "Communication Protocol for SOC HW/SW Co-Emulation System," Microelectronics, Vol. 40, No. 2, pp. 177-181, April 2010.
8. Yongbo Liao, Ping Li, Aiwu Ruan, Wenchang Li, Wei Li, "Design of Area-Efficient FIR Filter Based on ALU Architecture," Microelectronics, Vol. 40, No. 3, pp. 358-361, June 2010.
9. Yongbo Liao, Su Liu, Ping Li, "Design of Novel Power IC Over-current Protection Circuit," Power Electronics, Vol. 40, No. 5, pp. 133-134, October, 2006.
10. Yang Yang, Aiwu Ruan, Yongbo Liao, Wenjie Wu, "An FPGA-optimized high resolution time-to-digital converter array," Application of Electronic Technique, Vol. 37, No. 2, pp. 42-45,  2011.
11. Wenchang Li, Ping Li, Aiwu Ruan, Zhiming Yang, Yongbo Liao, Wei Li, "A Testing and Locating Approach for RAMs in FPGA," Microelectronics, Vol. 41, No. 4, pp. 608-611, August 2011.
12. Wenchang Li, Ping Li, Zhiming Yang, Aiwu Ruan, Yongbo Liao, Wei Li, "A Novel Approach to Fault Testing and Diagnosis of FPGA," Microelectronics, Vol. 41, No. 5, pp. 754-758, October 2011.
13. Chuanyin Xiang, Aiwu Ruan, Wenchang Li, Lin Wang, Yongbo Liao, "Fault mapping based algorithm for fault detection and diagnosis of the interconnects in SRAM-based FPGAs," Chinese Journal of Scientific Instrument, Vol. 32, No. 9, pp. 2010-2015, September 2011.
14. Jiaxin Ju, Jinfang Zhang, Yongbo Liao, Jiaming Bao, Bing Yang,"Design of Hysteresis Comparator with High Common Mode Input Level," Semiconductor Technology, Vol. 36, No. 8, pp. 623-626, August 2011.
15. Ping Li, Yongbo Liao, Aiwu Ruan, Wei Li, Wen-chang Li, "Novel Approach to Test Field Programmable Gate Array Based on SoC HW/SW Co-Verification Technology," Journal of University of Electronic Science and Technology of China, Vol. 38, No. 5, pp. 716-720, September 2009.
16. Yike Li, Yongbo Liao, Ping Li, "A Curvature Coefficient Canceled High Precision Low Temperature Drift CMOS Bandgap Reference," China Integrated Circuit, pp. 63-66, April 2008.
17. Tao Zhang,  Yike Li, Yongbo Liao ,"CMOS Band-Gap Voltage Reference of Zero Temperature Coefficients with UVLO Function," Journal of University of Electronic Science and Technology of China, Vol. 37, suppl, pp. 118-121, June 2008.
18. Kai Liu, Ping Li, Yongbo Liao, "Design of SCE-MI Transaction-Based SoC Co-Emulation Platform," Microelectronics, Vol. 37, No. 5, pp. 624-627, October 2007.
19. Zhiquan Yan, Ping Li, Yongbo Liao, "Design of Post-Stage Circuit in Digital Audio Power Amplifier based on Ternary Modulation," Audio Engineering, Vol. 31, No. 6, pp. 27-33, 2007.
20. Jing Guo, Yongbo Liao, Ping Li, "Electromagnetic Compatibility Design of 10-Million-Gate-Level IP Verification and Quality Assessment & Measurement Specific Platform," Microelectronics, Vol. 37, No. 5, pp. 656-659, October 2007.
21. Xiaoyi Wei, Ping Li, Yongbo Liao, Yuming Jia, "Co-verification methodology of SoC hardware and software based on transaction level," Journal of Shanxi University of Technology, Vol. 22, No. 2, pp. 42-45, June 2006.
Refereed Conference Publications
22. Y.B.Liao, Y.H. Wang and M. Yang, “A Temperature Compensation Circuit within Constant Current Charging Cycle”, Applied Mechanics and Materials Vols. 513-517, pp 4589-4592, 2014
23. Y.B.Liao, A.W.Ruan, Y. Wang, etc. “Interconnect Resources Multiple Faults Testing and Diagnosis in Field Programmable Gate Arrays”, 2012 4th International Conference on Environmental Science and Information Application Technology(ESIAT), pp.665-670, 2012.
24. Liao Yongbo, Ruan Aiwu, Wang Yu, Xiang Chuanyin , Wang Lin, Huang Haocheng , Zhu Jianhua,” Interconnect resources testing and faults diagnosis in field programmable gate arrays”, Electronic Measurement & Instruments (ICEMI), pp. 185 – 189, 2011
25. Y. B. Liao, P. Li, A. W. Ruan, W. Li, W. C. Li, "Full coverage location of logic resource faults in A SOC co-verification technology based FPGA functional test environment, " IEEE 8th International Conference on ASIC, pp. 1228-1231, 2009.
26. Y. B. Liao, P. Li, A. W. Ruan, Y. W. Wang, W. C. Li, "A HW/SW Co-Verification Technique for Field Programmable Gate Array (FPGA) Test, " IEEE Circuits and Systems International Conference on Testing and Diagnosis, pp. 1-4 , 2009.
27. Y. B. Liao, P. Li, A. W. Ruan, W. Li, W. C. Li, "Full coverage manufacturing testing for SRAM-based FPGA, " International Symposium on Integrated Circuits, pp. 478-481, 2009.
28. Y. B. Liao, P. Li, A. W. Ruan, Y. W. Wang, W. C. Li, W. Li, "Hierarchy Communication Channel in Transaction-Level Hardware/Software Co-emulation System, " International Workshop on Microprocessor Test and Verification, pp. 94-99, 2008.
29. Yongbo Liao, Zhangwei Lei, Ping Li,” Performance evaluations of 3rd order sigma-delta (Σ - Δ) modulators via ASIC implementation”, Communications, Circuits and Systems and West Sino Expositions, pp. 1540 – 1542, 2002.
30. Haocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Pin Li, "A new event driven testbench synthesis engine for FPGA emulation, " International Conference on ASIC (ASICON), pp 373-376, 2011.
31. A. W. Ruan, H. C. Huang, C. Q. Li, Z. J. Song, Y. B. Liao, W. Tang, "Debugging methodology for a synthesizable testbench FPGA emulator, " International Symposium on Integrated Circuits (ISIC), pp. 593-596, 2011.
32. A. W. Ruan, C. Q. Li, Z. J. Song, J. Chen, L. X. Deng, H. C. Hou, Y. B. Liao, "The third generation verification technology based SOC debugging, " International Conference on Computational Problem-Solving (ICCP), pp. 109-114, 2011.
33. A. W. Ruan, C. Q. Li, Z. J. Song, J. Chen, L. X. Deng, H. C. Hou, Y. B. Liao, "The third generation verification technology based SOC debugging, " International Conference on Computational Problem-Solving (ICCP), pp. 109-114, 2011.
34. A. W. Ruan,  Y. Wang, K. Shi, Z. J. Zhu, Q. Wu, X. Han, Y. B. Liao, "SOC HW/SW co-verification technology for application of FPGA test and diagnosis, " International Conference on Computational Problem-Solving (ICCP), pp. 1-6, 2011.
35. A. W. Ruan, H. C. Huang, C. Q. Li, Z. J. Song, Y. B. Liao, W. Tang, "Debugging methodology for a synthesizable testbench FPGA emulator, " International Symposium on Integrated Circuits (ISIC), pp. 593-596, 2011.
36. X. Cheng, A. W. Ruan, Y. B. Liao, P. Li, H. C. Huang, "A run-time RTL debugging methodology for FPGA-based co-simulation, " International Conference on Communications, Circuits and Systems (ICCCAS), pp. 891-895, 2010.
37. A. W. Ruan, Y. B. Liao, P. Li, Y. W. Wang, W. C. Li, "A Stream-Mode Based HW/SW Co-Emulation System for SOC Test and Verification, "IEEE Circuits and Systems International Conference, pp. 1-4, 2009.
38. A. W. Ruan, Y. B. Liao, P. Li, J. X. Li, "An ALU-based universal architecture for FIR filters, " International Conference on Communications, Circuits and Systems, pp. 1070-1073, 2009.
39. A. W. Ruan, Y. B. Liao, P. Li, W. C. Li, W. Li, "An improved data communication mechanism for a SOC hardware/software co-emulation environment, " International Conference on Communications, Circuits and Systems, pp. 1029-1032, 2009.
40. A. W. Ruan, Y. B. Liao,  P. Li, W. Li, W. C. Li, "Automatic configuration generation for a SOC co-verification technology based FPGA functional test system, " IEEE 8th International Conference on ASIC, pp. 605-608, 2009.
41. A. W. Ruan, Y. B. Liao, P. Li, W. C. Li, W. Li, "A self-defined communication protocol of transport layer in hierarchy transaction - level architecture for SOC verification, " International Conference on Communications, Circuits and Systems, pp. 1019-1023, 2009.
42. A. W. Ruan, Y. B. Liao, P. Li,  W. Li, W. C. Li, "An automatic test approach for field programmable gate array (FPGA), " International Symposium on Integrated Circuits, pp. 474-477, 2009.
43. A. W. Ruan, Y. B. Liao, P. Li, W. C. Li, W. Li, "Throughput estimation for ModelSim simulator tool based HW/SW co-verification system, " International Conference on Communications, Circuits and Systems, pp. 1014-1018, 2009.
44. FPGA configurable logic blocks verification method and system, China Patent No 200710050261.4
45. Wireless charging system of reflecting the communication way, China Patent No 201310268273.X
Books: Liao Yongbo and Ju Jiaxin, The power management chip design tutorial, Metallurgical Industry Press, ISBN 978-7-5024-5922-2, May 2012.
Liao Yongbo and Ju Jiaxin, Aether practical tutorial, Metallurgical Industry Press, ISBN ISBN 978-7-5024-7093-7, Jan 2016.